/**
 * Copyright (C) 2021 - 2031 O-Cubes Co., Ltd.
 */

/****************************************************************
 *  @file    dw_uart.h
 *  @brief   Designware uart driver header
 *  @version v1.0
 *  @date    03. Apr. 2023
 ****************************************************************/

#ifndef __DW_UART_H__
#define __DW_UART_H__

#include <stdint.h>
#include "dev_uart.h"
//#include "irq.h"

#ifdef __cplusplus
extern "C" {
#endif

/**
 * if this header file is included,
 * will indicate that this designware uart device
 * is used
 */
#define DEVICE_USE_DESIGNWARE_UART

/**
 * contains definitions of DesignWare UART register structure.
 */
/**
 * \brief	DesignWare UART register structure
 * \details	Detailed struct description of DesignWare UART
 * 	block register information, implementation of dev_uart_info::uart_regs
 */
typedef volatile struct dw_uart_reg {
	uint32_t DATA;          /*!< data in/out and DLL */
	uint32_t IER;           /*!< Interrupt enable register and DLH */
	uint32_t IIR;           /*!< Interrupt Id register and FCR */
	uint32_t LCR;           /*!< Line control Register */
	uint32_t MCR;           /*!< Modem control register */
	uint32_t LSR;           /*!< Line Status Register */
	uint32_t MSR;           /*!< Modem status Register */
	uint32_t SCRATCHPAD;    /*!< Uart scratch pad register */
	uint32_t LPDLL;         /*!< Low Power Divisor Latch (Low) Reg */
	uint32_t LPDLH;         /*!< Low Power Divisor Latch (High) Reg */
	uint32_t RES1[2];       /*!< Reserved */
	uint32_t SHR[16];       /*!< Shadow data register(SRBR and STHR) */
	uint32_t FAR;           /*!< FIFO Access register */
	uint32_t TFR;           /*!< Transmit FIFO Read */
	uint32_t RFW;           /*!< Receive FIFO write */
	uint32_t USR;           /*!< UART status register */
	uint32_t TFL;           /*!< Transmit FIFO level */
	uint32_t RFL;           /*!< Receive FIFO level */
	uint32_t SRR;           /*!< Software reset register */
	uint32_t SRTS;          /*!< Shadow request to send */
	uint32_t SBCR;          /*!< Shadow break control */
	uint32_t SDMAM;         /*!< Shadow DMA mode */
	uint32_t SFE;           /*!< Shadow FIFO enable */
	uint32_t SRT;           /*!< Shadow RCVR Trigger */
	uint32_t STET;          /*!< Shadow TX empty register */
	uint32_t HTX;           /*!< Halt TX */
	uint32_t DMASA;         /*!< DMA Software ACK */
	uint32_t RES2[18];      /*!< Reserved */
	uint32_t CPR;           /*!< Camponent parameter register */
	uint32_t UCV;           /*!< UART Component Version */
	uint32_t CTR;           /*!< Component typw register */
} DW_UART_REG, *DW_UART_REG_PTR;

#define DW_UART_GINT_DISABLED   (0)             /*!< designware interrupt disabled for control uart irq/fiq */
#define DW_UART_GINT_ENABLE     (1 << 0)        /*!< designware interrupt enabled for control uart irq/fiq */
#define DW_UART_TXINT_ENABLE    (1 << 1)        /*!< designware interrupt enabled for control transmit process */
#define DW_UART_RXINT_ENABLE    (1 << 2)        /*!< designware interrupt enabled for control transmit process */

#define DW_UART_INVALID_INTNO           (DEV_INTNO_INVALID)

#ifndef irq_handler
   typedef void (*irq_handler) (void *ptr);
#endif
/**
 * \brief	DesignWare UART control structure definition
 * \details	implement of dev_uart_info::uart_ctrl
 */
typedef struct dw_uart_ctrl {
	uint32_t id;                            /*!< uart id */
	uint32_t dw_uart_regbase;               /*!< uart ip register base */
	uint32_t dw_apb_bus_freq;               /*!< uart ip apb bus frequency */
	uint32_t intno;                         /*!< uart interrupt vector number */
	irq_handler dw_uart_int_handler;        /*!< uart interrupt handler */
	uint32_t tx_fifo_len;                   /*!< transmit fifo length, set by user in object implementation */
	uint32_t rx_fifo_len;                   /*!< receive fifo length, set by user in object implementation */
	uint32_t int_status;                    /*!< interrupt status for designware uart */
} DW_UART_CTRL, *DW_UART_CTRL_PTR;

int32_t dw_uart_open(DEV_UART *uart_dev, uint32_t baud);
int32_t dw_uart_close(DEV_UART *uart_dev);
int32_t dw_uart_control(DEV_UART *uart_dev, uint32_t ctrl_cmd, void *param);
int32_t dw_uart_write(DEV_UART *uart_dev, const void *data, uint32_t len);
int32_t dw_uart_read(DEV_UART *uart_dev, void *data, uint32_t len);
void dw_uart_isr(DEV_UART *uart_dev, void *ptr);
int32_t dw_uart_dma_write(DEV_UART *uart_dev, void *data, uint32_t len);
int32_t dw_uart_dma_read(DEV_UART *uart_dev, void *data, uint32_t len);

#ifdef __cplusplus
}
#endif

#endif /* __DW_UART_H__ */


